Does VHDL allow port mapping of a single bit output to multiple bits driven to same value, in one line?

For this hypothetical entity:

entity test is
  port (
    a_out: std_logic
end entity;

The a_out must drive three signals to the same value where the test entity is instantiated. Now one can create an std_logic signal and port map it to a_out and then drive the other three signals from this port mapped signal. Something like this:

signal bit_signal : std_logic;
signal x : std_logic;
signal y : std_logic;
signal z : std_logic;

test_i: test
  port map (
  a_out => bit_signal

x <= bit_signal; 
y <= bit_signal;
z <= bit_signal;

It would be great if the intermediate bit_signal is not required and the a_out can directly drive the signals x, y, z doing something like this:

test_i: test
  port map (
  a_out => x, y, z

I don’t think VHDL 2008 allows this, I cannot say anything about the VHDL 2019 though.

Electrical Engineering Asked on November 11, 2021

1 Answers

One Answer

You could try using alias, something like this:

signal x: std_logic;
alias y is x;
alias z is x;

test_i: test
  port map (
  a_out => x

Answered by tim on November 11, 2021

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